PARITY ERROR DETECTION VERIFICATION

Patent №

US 8,635,566

Granted

2014-01-21

Filed 2011

Owner

ADVANCED MICRO DEVICES, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13331172

A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.

AI hardwareG06F 30/33G06F 2117/02

AI classification

AI hardware0.97
Planning0.18
Natural language0.01
Evolutionary computation0.00
Knowledge representation0.00
Vision0.00
Machine learning0.00
Speech0.00

Ownership

ADVANCED MICRO DEVICES, INC.

assignment · 274210341

Assignors

HSIONG, CHRISTOPHER E.

On an employer assignment, the assignors are typically the inventors.

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