INTEGRATING MULTIPLE FPGA DESIGNS BY MERGING CONFIGURATION SETTINGS

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.