CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE

Patent №

US 8,773,944

Granted

2014-07-08

Filed 2012

Owner

QUALCOMM INCORPORATED

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13368752

An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.

AI hardwareG11C 8/10G06F 12/0207G11C 8/16H03M 13/2707H03M 13/2764

AI classification

AI hardware1.00
Vision0.01
Natural language0.00
Machine learning0.00
Speech0.00
Evolutionary computation0.00
Knowledge representation0.00
Planning0.00

Ownership

QUALCOMM INCORPORATED

assignment · 290000760

Assignors

CHEN, CHIHTUNG, KANG, INYUP, CHAIYAKUL, VIRAPHOL

On an employer assignment, the assignors are typically the inventors.

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