DETECTING DEFECTS ON A WAFER

Patent №

US 8,775,101

Granted

2014-07-08

Filed 2011

Owner

KLA-TENCOR CORPORATION

Lab

—

AI components

vision

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13196758

View graph

Methods and systems for detecting defects on a wafer are provided.

VisionG01R 31/28G01N 21/9501G01N 21/956

Google Patents

AI classification

Vision0.97

Natural language0.01

Machine learning0.00

Evolutionary computation0.00

AI hardware0.00

Knowledge representation0.00

Planning0.00

Speech0.00

Ownership

KLA-TENCOR CORPORATION

assignment · 269780018

Assignors

HUANG, JUNQING, ZHANG, YONG, CHEN, STEPHANIE, LUO, TAO, GAO, LISHENG, WALLINGFORD, RICHARD

On an employer assignment, the assignors are typically the inventors.

From the same owner

INSPECTION OF RETICLES USING MACHINE LEARNINGUS 12,094,101 · 2024 Systems and Methods for Metrology with Layer-Specific Illumination SpectraUS 11,852,590 · 2023 Bandgap Measurements of Patterned Film Stacks Using Spectroscopic MetrologyUS 11,796,390 · 2023 APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR DEFECT DETECTION IN WORK PIECESUS 11,726,126 · 2023 CROSS LAYER COMMON-UNIQUE ANALYSIS FOR NUISANCE FILTERINGUS 11,694,327 · 2023 Computer Assisted Weak Pattern Detection and Quantification SystemUS 11,688,052 · 2023 Multimode Defect Classification in Semiconductor InspectionUS 11,668,655 · 2023 ACCELERATED TRAINING OF A MACHINE LEARNING BASED MODEL FOR SEMICONDUCTOR APPLICATIONSUS 11,580,375 · 2023

Cites (137)

SYSTEMS AND METHODS FOR CREATING PERSISTENT DATA FOR A WAFER AND FOR USING PERSISTENT DATA FOR INSPECTION-RELATED FUNCTIONSUS 8,126,255 · 2012 COMPUTER-IMPLEMENTED METHODS, COMPUTER-READABLE MEDIA, AND SYSTEMS FOR IDENTIFYING ONE OR MORE OPTICAL MODES OF AN INSPECTION SYSTEM AS CANDIDATES FOR USE IN INSPECTION OF A LAYER OF A WAFERUS 8,073,240 · 2011 WAFER EDGE DEFECT INSPECTION USING CAPTURED IMAGE ANALYSISUS 7,968,859 · 2011 DETERMINING LOCATIONS ON A WAFER TO BE REVIEWED DURING DEFECT REVIEWUS 7,904,845 · 2011 METHOD AND APPARATUS FOR PROVIDING SECURE INTELLECTUAL PROPERTY CORES FOR A PROGRAMMABLE LOGIC DEVICEUS 7,890,917 · 2011 SYSTEMS AND METHODS FOR CREATING INSPECTION RECIPESUS 7,877,722 · 2011 GROUPING SYSTEMATIC DEFECTS WITH FEEDBACK FROM ELECTRICAL INSPECTIONUS 7,760,929 · 2010 METHODS FOR DETECTING AND CLASSIFYING DEFECTS ON A RETICLEUS 7,738,093 · 2010 METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATAUS 7,676,077 · 2010 METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATAUS 7,570,796 · 2009 DEVICE AND METHOD FOR INSPECTING PHOTOMASKS AND PRODUCTS FABRICATED USING THE SAMEUS 7,424,145 · 2008 METHOD AND APPARATUS FOR INSPECTING PATTERN DEFECTSUS 7,388,979 · 2008 SYSTEM AND METHOD FOR TROUBLESHOOTING SOFTWARE CONFIGURATION PROBLEMS USING APPLICATION TRACINGUS 7,386,839 · 2008 APPARATUS FOR INSPECTING WAFER SURFACE, METHOD FOR INSPECTING WAFER SURFACE, APPARATUS FOR JUDGING DEFECTIVE WAFER, METHOD FOR JUDGING DEFECTIVE WAFER, AND APPARATUS FOR PROCESSING INFORMATION ON WAFER SURFACEUS 7,383,156 · 2008 METHODS AND SYSTEMS FOR RETICLE INSPECTION AND DEFECT REVIEW USING AERIAL IMAGINGUS 7,379,175 · 2008 AUTOMATIC ALIGNMENT OF INTEGRATED CIRCUIT AND DESIGN LAYOUT OF INTEGRATED CIRCUIT TO MORE ACCURATELY ASSESS THE IMPACT OF ANOMALIESUS 7,194,709 · 2007 CHARACTERIZATION AND VERIFICATION FOR INTEGRATED CIRCUIT DESIGNSUS 7,174,520 · 2007 METHOD AND APPARATUS FOR SYNCHRONIZING DATA ACQUISITION OF A MONITORED IC FABRICATION PROCESSUS 7,171,334 · 2007 PROGRESSIVE SELF-LEARNING DEFECT REVIEW AND CLASSIFICATION METHODUS 7,162,071 · 2007 DUMMY FILL FOR INTEGRATED CIRCUITSUS 7,152,215 · 2006 METHODS AND SYSTEMS FOR INSPECTING RETICLES USING AERIAL IMAGING AND DIE-TO-DATABASE DETECTIONUS 7,123,356 · 2006 DUMMY FILL FOR INTEGRATED CIRCUITSUS 7,124,386 · 2006 SYSTEM AND METHOD FOR LITHOGRAPHY SIMULATIONUS 7,120,895 · 2006 SYSTEM AND METHOD FOR LITHOGRAPHY SIMULATIONUS 7,117,477 · 2006 SYSTEM AND METHOD FOR LITHOGRAPHY SIMULATIONUS 7,117,478 · 2006

and 112 more

Cited by (17)

IC With Test Structures Embedded Within A Contiguous Standard Cell AreaUS 10,777,472 · 2020 GENERATING SIMULATED OUTPUT FOR A SPECIMENUS 10,043,261 · 2018 INTEGRATED CIRCUIT INCLUDING NCEM-ENABLED, CORNER GAP-CONFIGURED FILL CELLS, WITH NCEM PADS FORMED FROM AT LEAST THREE CONDUCTIVE STRIPES POSITIONED BETWEEN ADJACENT GATESUS 9,911,668 · 2018 Integrated Circuit Including NCEM-Enabled, Diagonal Gap-Configured Fill Cells, with NCEM Pads Formed from at Least Three Conductive Stripes Positioned Between Adjacent GatesUS 9,911,669 · 2018

Related research

Application of deep learning-based wafer defect detectionSemantic Scholar Machine Learning-Based Detection Method for Wafer Test Induced DefectsSemantic Scholar PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning TechniquesSemantic Scholar Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect DiagnosisSemantic Scholar Generative Models Based Wafer Surface Defect Detection in Limited Sample ScenariosSemantic Scholar

Full text

Google Patents