COMPILER OPTIMIZED SAFETY MECHANISM

Patent №

US 8,935,679

Granted

2015-01-13

Filed 2012

Owner

FREESCALE SEMICONDUCTOR, INC.

Lab

AI components

2

planning · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13648501

An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.

AI classification

AI hardware0.97
Planning0.64
Knowledge representation0.02
Natural language0.01
Evolutionary computation0.00
Machine learning0.00
Speech0.00
Vision0.00

Ownership

FREESCALE SEMICONDUCTOR, INC.

assignment · 291040602

Assignors

MORRISON, GARY R., KAHNE, BRIAN C., REIPOLD, ANTHONY M.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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