HIERARCHICAL FINITE STATE MACHINE GENERATION FOR POWER STATE BEHAVIOR IN AN ELECTRONIC DESIGN
Patent №
US 8,943,451
Granted
2015-01-27
Filed 2011
Owner
MENTOR GRAPHICS CORPORATION
Lab
—
AI components
1
kr
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13167415
The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification.
AI classification
Ownership
MENTOR GRAPHICS CORPORATION
assignment · 323480913
Assignors
DWIVEDI, PANKAJ K, SRIVASTAVA, AMIT, KAKKAR, SACHIN, MUKHERJEE, RUDRA
On an employer assignment, the assignors are typically the inventors.