Patent №
US 8,949,754
Granted
2015-02-03
Filed 2013
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14108902
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using a processor, a low-power electronic design and determining if a power domain associated with the low-power electronic design is active. The method may further include identifying, at a register transfer level (RTL) at least one X value associated with an active power domain wherein identifying occurs during a simulation.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 317990969
Assignors
SHARMA, AMIT, AGGARWAL, AMIT, RAHEJA, ABHISHEK, CHOPRA, MANU
On an employer assignment, the assignors are typically the inventors.