SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS OF IN-ORDER AND OUT-OF-ORDER EXECUTION QUEUES

Patent №

US 9,110,656

Granted

2015-08-18

Filed 2011

Owner

FREESCALE SEMICONDUCTOR, INC.

Lab

AI components

2

nlp · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13210566

A processor configured to provide instructions of a first instruction type to a first execution unit, and a second execution queue configured to provide instructions of a second instruction type to a second execution unit. A first instruction of the second instruction type is received. The first instruction is decoded by the decode/issue unit to determine operands of the first instruction. The operands of the first instruction are determined to include a dependency on a second instruction of the first instruction type stored in a first entry of the first execution queue. The first instruction is stored in a first entry of the second execution queue. A synchronization indicator corresponding to the first instruction in a second entry of the first execution queue is set immediately adjacent the first entry of the first execution queue, which indicates that the first instruction is stored in another execution queue.

Natural languageAI hardwareG06F 9/30087G06F 9/3814G06F 9/3824G06F 9/3838G06F 9/3851G06F 9/3891

AI classification

AI hardware0.85
Natural language0.50
Knowledge representation0.04
Planning0.00
Vision0.00
Evolutionary computation0.00
Speech0.00
Machine learning0.00

Ownership

FREESCALE SEMICONDUCTOR, INC.

assignment · 267710704

Assignors

TRAN, THANG M., NGUYEN, TRINH HUY H., TRAN, THANG M., NGUYEN, TRINH HUY H.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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