SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS OF IN-ORDER AND OUT-OF-ORDER EXECUTION QUEUES
Patent №
US 9,110,656
Granted
2015-08-18
Filed 2011
Owner
FREESCALE SEMICONDUCTOR, INC.
Lab
—
AI components
2
nlp · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13210566
A processor configured to provide instructions of a first instruction type to a first execution unit, and a second execution queue configured to provide instructions of a second instruction type to a second execution unit. A first instruction of the second instruction type is received. The first instruction is decoded by the decode/issue unit to determine operands of the first instruction. The operands of the first instruction are determined to include a dependency on a second instruction of the first instruction type stored in a first entry of the first execution queue. The first instruction is stored in a first entry of the second execution queue. A synchronization indicator corresponding to the first instruction in a second entry of the first execution queue is set immediately adjacent the first entry of the first execution queue, which indicates that the first instruction is stored in another execution queue.
AI classification
Ownership
FREESCALE SEMICONDUCTOR, INC.
assignment · 267710704
Assignors
TRAN, THANG M., NGUYEN, TRINH HUY H., TRAN, THANG M., NGUYEN, TRINH HUY H.
On an employer assignment, the assignors are typically the inventors.