BACKGROUND REORDERING - A PREVENTIVE WEAR-OUT CONTROL MECHANISM WITH LIMITED OVERHEAD

Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed.