Patent №
US 9,348,587
Granted
2016-05-24
Filed 2013
Owner
HYPERION CORE, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
13809159
The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
AI hardwareG06F 9/3838G06F 9/3001G06F 9/30043G06F 9/30054G06F 9/30058G06F 9/30065G06F 9/30072G06F 9/30076+18 more
AI classification
AI hardware1.00
Machine learning0.17
Natural language0.02
Knowledge representation0.02
Speech0.01
Vision0.00
Planning0.00
Evolutionary computation0.00
Ownership
HYPERION CORE, INC.
assignment · 342900711
Assignors
VORBACH, MARTIN
On an employer assignment, the assignors are typically the inventors.
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