MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

Technology is disclosed for designing a prototype including a plurality of programmable chips for modelling a logic design comprising a hierarchy of logic modules. An example method includes: creating a new hierarchy of logic modules on the basis of the hierarchy of the logic modules of the logic design, by flattening the modules that cannot be preserved according to design constraints; partitioning the new hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimizing: inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; and the number of crossings of programmable chips of a critical combinatorial path; and establishing a routing of the signals between programmable chips using the physical resources available.