TRANSACTION ABORT INSTRUCTION

Patent №

US 9,529,598

Granted

2016-12-27

Filed 2013

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

Lab

IBM Research

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13789999

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A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.

AI hardwareG06F 9/3861G06F 9/30087G06F 9/30101G06F 9/3834G06F 9/38585G06F 9/3863

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AI hardware0.99

Natural language0.05

Speech0.00

Machine learning0.00

Knowledge representation0.00

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Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 299490675

Assignors

GREINER, DAN F., JACOBI, CHRISTIAN, MITRAN, MARCEL, SLEGEL, TIMOTHY J.

On an employer assignment, the assignors are typically the inventors.

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Cites (61)

HANDLING AND PROCESSING OF MASSIVE NUMBERS OF PROCESSING INSTRUCTIONS IN REAL TIMEUS 8,612,299 · 2013 PROCESSOR WITH LAST BRANCH RECORD REGISTER STORING TRANSACTION INDICATORUS 8,479,053 · 2013 DISTRIBUTED TRANSACTION MANAGEMENT USING TWO-PHASE COMMIT OPTIMIZATIONUS 8,442,962 · 2013 METHOD AND SYSTEM FOR DIVIDING AND EXECUTING ON-LINE TRANSACTION PROCESSING IN DISTRIBUTED ENVIRONMENTUS 8,276,153 · 2012 HARDWARE ACCELERATED TRANSACTIONAL MEMORY SYSTEM WITH OPEN NESTED TRANSACTIONSUS 8,229,907 · 2012 CONTROLLING EXECUTION OF TRANSACTIONSUS 8,161,016 · 2012 SYSTEM AND METHOD FOR IMPLEMENTING NONBLOCKING ZERO-INDIRECTION TRANSACTIONAL MEMORYUS 8,140,497 · 2012 PIPELINE REPLAY SUPPORT FOR MULTICYCLE OPERATIONSUS 8,117,423 · 2012 METHOD AND APPARATUS FOR IMPROVING TRANSACTIONAL MEMORY COMMIT LATENCYUS 8,041,900 · 2011 SYSTEM AND METHOD FOR SUPPORTING PHASED TRANSACTIONAL MEMORY MODESUS 7,966,459 · 2011 METHOD AND APPARATUS FOR SYNCHRONIZING THREADS ON A PROCESSOR THAT SUPPORTS TRANSACTIONAL MEMORYUS 7,930,695 · 2011 SYSTEM AND METHOD FOR ALLOCATING AND DEALLOCATING MEMORY WITHIN TRANSACTIONAL CODEUS 7,908,456 · 2011 FRAMEWORK FOR HANDLING BUSINESS TRANSACTIONSUS 7,904,434 · 2011 PARALLEL NESTED TRANSACTIONS IN TRANSACTIONAL MEMORYUS 7,890,472 · 2011 ABORT PRIORITIZATION IN A TRACE-BASED PROCESSORUS 7,870,369 · 2011 CONCURRENT ATOMIC EXECUTIONUS 7,865,701 · 2011 COLLISION RECOGNITION DEVICE FOR A VEHICLEUS 7,840,323 · 2010 CHECKING FOR EXCEPTION BY FLOATING POINT INSTRUCTION REORDERED ACROSS BRANCH BY COMPARING CURRENT STATUS IN FP STATUS REGISTER AGAINST LAST STATUS COPIED IN SHADOW REGISTERUS 7,840,788 · 2010 DYNAMIC CONCURRENT ATOMIC EXECUTIONUS 7,836,280 · 2010 VERIFICATION OF MEMORY CONSISTENCY AND TRANSACTIONAL MEMORYUS 7,814,378 · 2010 REDUCING THE SIZE OF A DATA STREAM PRODUCED DURING INSTRUCTION TRACINGUS 7,707,394 · 2010 TECHNIQUE TO ALLOW A FIRST TRANSACTION TO WAIT ON CONDITION THAT AFFECTS ITS WORKING SETUS 7,703,098 · 2010 METHODS AND APPARATUS TO IMPLEMENT PARALLEL TRANSACTIONSUS 7,669,015 · 2010 METHOD AND APPARATUS FOR EXECUTING A LONG TRANSACTIONUS 7,669,040 · 2010 METHOD AND APPARATUS FOR REPORTING FAILURE CONDITIONS DURING TRANSACTIONAL EXECUTIONUS 7,617,421 · 2009

and 36 more

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