DRAM ERROR CORRECTION EVENT NOTIFICATION

Patent №

US 9,529,667

Granted

2016-12-27

Filed 2014

Owner

INTEGRATED SILICON SOLUTION, INC.

Lab

AI components

1

evo

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14279113

A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

AI classification

Evolutionary computation0.85
Planning0.10
Knowledge representation0.02
Vision0.02
AI hardware0.00
Natural language0.00
Machine learning0.00
Speech0.00

Ownership

INTEGRATED SILICON SOLUTION, INC.

assignment · 329070011

Assignors

ZASTROW, LYN R.

On an employer assignment, the assignors are typically the inventors.

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