BRANCH PREDICTION POWER REDUCTION

Patent №

US 9,547,358

Granted

2017-01-17

Filed 2012

Owner

NVIDIA CORPORATION

Lab

NVIDIA AI

AI components

kr · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13458513

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In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.

Knowledge representation AI hardwareG06F 1/3243G06F 9/30058G06F 9/323Y02D 10/00

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AI hardware1.00

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Ownership

NVIDIA CORPORATION

assignment · 281220766

Assignors

AGGARWAL, ANEESH, SEGELKEN, ROSS, WASSON, PAUL

On an employer assignment, the assignors are typically the inventors.

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Cites (30)

SYSTEM AND METHOD FOR HIGH PERFORMANCE, POWER EFFICIENT STORE BUFFER FORWARDINGUS 8,775,740 · 2014 PROGRAMMABLE CACHE ACCESS PROTOCOL TO OPTIMIZE POWER CONSUMPTION AND PERFORMANCEUS 8,458,404 · 2013 METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICEUS 8,352,683 · 2013 CACHE MEMORY SYSTEM FOR A DATA PROCESSING APPARATUSUS 8,335,122 · 2012 METHOD AND SYSTEM FOR POWER CONSERVATION IN A HIERARCHICAL BRANCH PREDICTORUS 8,028,180 · 2011 STRUCTURE FOR POWER-EFFICIENT CACHE MEMORYUS 7,904,658 · 2011 POWER-PERFORMANCE MODULATION IN CACHES USING A SMART LEAST RECENTLY USED SCHEMEUS 7,689,772 · 2010 HIERARCHICAL MRU POLICY FOR DATA CACHEUS 7,536,510 · 2009 LOW-POWER CACHE SYSTEM AND METHODUS 7,487,369 · 2009 CACHE ORGANIZATION FOR POWER OPTIMIZED MEMORY ACCESSUS 7,475,192 · 2009 POWER COLLAPSE FOR A WIRELESS TERMINALUS 7,369,815 · 2008 METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION IN A CACHE MEMORYUS 7,360,023 · 2008 CACHE MEMORY AND METHOD OF OPERATIONUS 6,718,439 · 2004 METHOD AND SYSTEM FOR BRANCH TARGET PREDICTION USING PATH INFORMATIONUS 6,601,161 · 2003 Set-Associative cache memory having a built-in set prediction arrayUS 6,356,990 · 2002 METHOD AND APPARATUS FOR PERFORMING POWER MANAGEMENT BY SUPPRESSING THE SPECULATIVE EXECUTION OF INSTRUCTIONS WITHIN A PIPELINED MICROPROCESSORUS 6,282,663 · 2001 Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictionsUS 6,279,107 · 2001 MULTI-WAY CACHE EXPANION CIRCUIT ARCHITECTUREUS 6,148,374 · 2000 HARDWARE VIRTUAL MACHINE INSTRUCTION PROCESSORUS 6,021,469 · 2000 MULTIPROBE INSTRUCTION CACHE WITH INSTRUCTION-BASED PROBE HINT GENERATION AND TRAINNG WHEREBY THE CACHE BANK OR WAY TO BE ACCESSED NEXT IS PREDICTEDUS 5,933,860 · 1999 MICROPPROCESSOR SYSTEM WITH PROCESS IDENTIFICATION TAG ENTRIES TO REDUCE CACHE FLUSHING AFTER A CONTEXT SWITCHUS 5,809,522 · 1998 SLAVE CACHE HAVING SUB-LINE VALID BITS UPDATED BY A MASTER CACHEUS 5,784,590 · 1998 ARRAY HAVING AN UPDATE CIRCUIT FOR UPDATING A STORAGE LOCATION WITH A VALUE STORED IN ANOTHER STORAGE LOCATIONUS 5,687,110 · 1997 CACHE MEMORY CONTAINING EXTRA STATUS BITS TO INDICATE MEMORY REGIONS WHERE LOGGING OF DATA SHOULD OCCURUS 5,666,514 · 1997 MICROPROCESSOR CACHE MEMORY WAY PREDICTION BASED ON THE WAY OF PREVIOUS MEMORY READUS 5,640,532 · 1997

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