METHOD AND APPARATUS FOR SHARING INSTRUCTION SCHEDULING RESOURCES AMONG A PLURALITY OF EXECUTION THREADS IN A MULTI-THREADED PROCESSOR ARCHITECTURE

A microprocessor includes a front end module and a schedule queue module. The front end module is configured to retrieve first instructions, corresponding to a first thread, from an instruction cache, and retrieve second instructions, corresponding to a second thread, from the instruction cache. The front end module is also configured to decode the first instructions into first decoded instructions, and decode the second instructions into second decoded instructions. The schedule queue module is configured to selectively store the first decoded instructions and the second decoded instructions from the front end module and, for each stored decoded instruction, selectively issue the stored decoded instruction to an execution module. The schedule queue is further configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a threshold.