INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY

Patent №

US 9,710,267

Granted

2017-07-18

Filed 2013

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

Lab

IBM Research

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13783335

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A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

AI hardwareG06F 9/30043G06F 9/3001G06F 9/3004G06F 9/30076G06F 9/355G06F 9/3824G06F 9/3861

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Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 299100989

Assignors

BRADBURY, JONATHAN D., GSCHWIND, MICHAEL K., JACOBI, CHRISTIAN, SCHWARZ, ERIC M, SLEGEL, TIMOTHY J.

On an employer assignment, the assignors are typically the inventors.

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Cites (32)

APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECHTURE ON A COMPUTER OF A SECOND ARCHITECHTUREUS 8,127,121 · 2012 COMPILING SCALAR CODE FOR A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) EXECUTION ENGINEUS 8,108,846 · 2012 COMPARING TEXT STRINGSUS 7,991,987 · 2011 SYSTEM AND METHOD FOR EFFICIENTLY EXECUTING SINGLE PROGRAM MULTIPLE DATA (SPMD) PROGRAMSUS 7,904,905 · 2011 ROTATE THEN OPERATE ON SELECTED BITS FACILITY AND INSTRUCTIONS THEREFOREUS 7,895,419 · 2011 METHOD AND APPARATUS FOR CONSTANT GENERATION IN SIMD PROCESSINGUS 7,689,811 · 2010 METHOD AND SYSTEM FOR PREFETCHING DATAUS 6,918,010 · 2005 SIMD DATAPATH COUPLED TO SCALAR/VECTOR/ADDRESS/CONDITIONAL DATA REGISTER FILE WITH SELECTIVE SUBPATH SCALAR PROCESSING MODEUS 6,839,828 · 2005 TRANSLATION AND TRANSFORMATION OF HETEROGENEOUS PROGRAMSUS 6,802,056 · 2004 ADDRESS GENERATING APPARATUS AND MOTION VECTOR DETECTORUS 6,662,288 · 2003 DATA COMPRESSION METHOD AND APPARATUS IMPLEMENTED WITH LIMITED LENGTH CHARACTER TABLES AND COMPACT STRING CODE UTILIZATIONUS 6,570,511 · 2003 METHOD AND APPARATUS FOR IMPLEMENTING EXECUTION PREDICATES IN A COMPUTER PROCESSING SYSTEMUS 6,513,109 · 2003 PERFORMANCE OF DATA STREAM TOUCH EVENTSUS 6,499,116 · 2002 DYNAMIC OPTIMIZING OBJECT CODE TRANSLATOR FOR ARCHITECTURE EMULATION AND DYNAMIC OPTIMIZING OBJECT CODE TRANSLATION METHODUS 6,463,582 · 2002 ARRAY ACCESS BOUNDARY CHECK BY EXECUTING BNDCK INSTRUCTION WITH COMPARISON SPECIFIERSUS 6,408,383 · 2002 METHOD AND APPARATUS FOR REORDERING MEMORY OPERATIONS ALONG MULTIPLE EXECUTION PATHS IN A PROCESSORUS 6,381,691 · 2002 Methods and apparatus for reordering and renaming memory references in a multiprocessor computer systemUS 6,349,361 · 2002 INFORMATION MANAGEMENT AND RETRIEVALUS 6,338,057 · 2002 METHOD AND APPARATUS FOR GENERATING ELEMENTS OF A SECOND VECTOR FROM A FIRST VECTOR BY GENERATING VECTOR ELEMENTS OF THE SECOND VECTOR FROM A TABLE WITH PRESELECTED OFFSETUS 6,334,176 · 2001 SYMMETRICAL MULTIPROCESSING BUS AND CHIPSET USED FOR COPROCESSOR SUPPORT ALLOWING NON-NATIVE CODE TO RUN IN A SYSTEMUS 6,308,255 · 2001 PIPELINE CONTROL FOR HIGH-FREQUENCY PIPELINED DESIGNSUS 6,192,466 · 2001 Forwarding stored Dara Fetched for out-of-order load/read operation to over-taken operation read-accessing same memory locationUS 6,189,088 · 2001 STORAGE BUFFER WITH DYNAMICALLY ADJUSTABLE BOUNDARIESUS 6,094,695 · 2000 PREPROCESSING OF STORED TARGET ROUTINES FOR EMULATING INCOMPATIBLE INSTRUCTIONS ON A TARGET PROCESSORUS 6,009,261 · 1999 INSTRUCTION METHODS FOR PERFORMING DATA FORMATTING WHILE MOVING DATA BETWEEN MEMORY AND A VECTOR REGISTER FILEUS 5,812,147 · 1998

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