SIMULTANEOUS INVALIDATION OF ALL ADDRESS TRANSLATION CACHE ENTRIES ASSOCIATED WITH X86 PROCESS CONTEXT IDENTIFI9-

A translation-lookaside buffer (TLB) includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector, wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID). The TLB also includes an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries. The TLB also includes logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector.