MEMORY ELEMENTS WITH DYNAMIC PULL-UP WEAKENING WRITE ASSIST CIRCUITRY

Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.