PREDICTIVE CAPACITANCE LAYOUT METHOD FOR INTEGRATED CIRCUITS

Patent №

US RE35671

Granted

1997-11-25

Filed 1996

Owner

Lab

AI components

2

planning · evo

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

08683618

A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.

AI classification

Planning0.90
Evolutionary computation0.57
Machine learning0.01
Knowledge representation0.01
AI hardware0.00
Natural language0.00
Vision0.00
Speech0.00
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