Design and Performance Evaluation of Dram Storage Arrays with Different Technologies

1T1C DRAM cell has been simulated using Tanner EDA tool over 180nm technology and array of 2*2 DRAM, 4*4 DRAM has also been simulated over 180nm. H-spice tool is also used to simulate 1KB DRAM memory over 22nm technology using two capacitors to reduce the leakage as well as 1T1C DRAM cell. Power consumption and delay are the important parameters to design any circuits. Hence, they are also computed with the retention time. Timing parameters such as row address to column address delay, row pre-charge time, latency time have also computed.