TESTCHIP DESIGN FOR PROCESS ANALYSIS IN SUB-MICRON DRAM FABRICATION

Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations. Several test structures are described which are formed from regions of the integrated circuit product itself. The structures are designed to monitor specific process steps where such local variations occur. The invention teaches the use of product specific test structures for process monitoring of sub-micron DRAM integrated circuits. The structures described are portions of the cell array outfitted with test probe pads and are capable of measuring opens and shorts in wordlines and bitlines. Another structure comprises a testable string of bitline contacts.