Patent US 4,037,089

An integrated circuit comprising a programmable logic array includes an AND-gate array and an OR-gate array connected thereto with column lines of the AND-gate array being shared in common with column lines of the OR-gate array. The AND-gate array and the OR-gate array are both operated dynamically, and a dynamically operated shift register is interconnected between an output of the OR-gate array and an input of the AND-gate array, to supply a feedback signal to the latter to realize sequential logic functions.