Patent №
US 4,528,634
Granted
1985-07-09
Filed 1982
Owner
HITACHI, LTD.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
06433405
A bit pattern generator includes two memories which are provided for storing a bit pattern for a scanning line produced from design data. When a bit pattern is created and stored in one of the memories, the previously created and stored bit pattern is read out from the other memory. For the creation of each bit pattern, a scanning line is divided into a plurality of bytes. Model patterns of bit patterns existing in the respective bytes are stored in a ROM. From the combination of start point and end point addresses specifying the byte positions and the ROM addresses, a ROM address for each byte is logically determined so that any model patterns in the ROM are sequentially stored in the first mentioned memories.
AI classification
Ownership
HITACHI, LTD.
assignment · 40570507
Assignors
NAKAHATA, KOZO, KAWAGUCHI, IKUO, YAMAGUCHI, KAZUO
On an employer assignment, the assignors are typically the inventors.