LOGIC SIMULATION APPARATUS

A logic simulation apparatus has a data memory for storing node level data of a logic circuit, a command memory for storing interconnection data which comprises an input data address, an output data address, a fan-out address and a function of module, and a data processing circuit for simulating the operation for each module in accordance with the commands read out from the command memory. The read address of the command memory is accessed by an address counter which is incremented by one for every read operation. The fan-out address read out from the command memory is written in an address queue, and when a simulation of one module is completed, the fan-out address is read out from the address queue and set in the address counter in order to start a simulation of a next module.