BUFFER APPARATUS FOR CONTROLLING ACCESS REQUESTS AMONG PLURAL MEMORIES AND PLURAL ACCESSING DEVICES

A request buffer apparatus controls a plurality of access requests to devices to be accessed (e.g., memory banks) commonly used by a plurality of accessing devices (e.g., a CPU, channels, and DMA units) in a data processing system. The apparatus has a request buffer means which has a plurality of buffers for storing the access requests. Write/read operations of the requests in and from the request buffer means are randomly performed in accordance with the status of the device to be accessed corresponding to the request stored in the buffer. Requests corresponding to the same device to be accessed are written in the empty buffers of the request buffer means in the order they are generated, and are read out from the request buffer means in the order that they are written. Each device to be accessed has a buffer write address generating means, and the buffer write status of each buffer is indicated so as to obtain the next buffer write address.