A DIVIDER CIRCUIT FOR DIVIDING N-BIT BINARY DATA USING DECIMAL SHIFFTING AND SUMMATION TECHNIQUES

A divider circuit for dividing n-bit binary data L.sub.n by a number m which is defined as m=2.sup.a -1 (a is a positive integer of 2 or more), wherein a division operation L.sub.n /m is developed into an infinite series given as: ##EQU1## for L.sub.(n-ba) =L.sub.n /2.sup.ba (where b is a positive integer). The divider circuit includes a first circuit responsive to the binary data L.sub.n, for sectioning a decimal part of each term of the infinite series in a unit of a-bit from a most significant bit of the decimal part, and for summing corresponding a-bit sectioned portions of decimal parts of all terms of the infinite series to generate summed decimal parts, a second circuit for discriminating a carry to an integer part of the binary data L.sub.n from the summed decimal parts, and a third circuit for adding the carry to a sum of integer parts of the binary data L.sub.n to provide divided data corresponding to L.sub.n /m.