DATA PROCESSING SYSTEM WITH CPU REGISTER TO REGISTER DATA TRANSFERS OVERLAPPED WITH DATA TRANSFER TO AND FROM MAIN STORAGE

The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit. Thus, the register to register data transfers within the CPU are overlapped with the data transfers over the I/O bus to main storage. The data transfers to and from main storage are generally considerably longer that the simpler register to register data transfer. The apparatus may be operated so that several register to register transfers may take place during the time required for a transfer of data to or from the external storage unit. The present invention further includes means for dynamically determining data dependencies between the register to register transfers and the I/O bus transfers.