ARITHMETIC CONTROL APPARATUS FOR A PIPELINE PROCESSING SYSTEM

A microprogram-controlled type arithmetic control apparatus which performs pipeline processing is provided. In the apparatus, a microinstruction corresponding to a macroinstruction to be processed are read out of a control storage at least one stage prior to an OF (operand fetch) stage. The microinstruction and data (source data) are respectively output onto a microinstruction bus and a data bus at the OF stage. By the beginning of an E (instruction execution) stage, data (source data) on the data bus and the microinstruction on the microinstruction bus are loaded into first and second registers, respectively. Then, at the beginning of the E stage, arithmetic operation by an arithmetic and logic unit can be performed immediately.