DRIVING CIRCUITRY FOR EEPROM MEMORY CELL

A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising four P-channel transistors and two N-channel transistors as well as four switches. The circuit comprises a two-transistor inverter with a feedback transistor and three isolating transistors that prevent excessive currents and voltages from damaging internal and external circuit components.