HORIZONTAL COMPUTER HAVING REGISTER MULTICONNECT FOR EXECUTION OF AN INSTRUCTION LOOP WITH RECURRANCE

A horizontal computer for executing a loop with recurrence. The computer features a horizontal architecture in which parallel processors repeatedly iterate a loop of instructions with recurrence, that is, where a result operand from one iteration is used as a source operand in a later iteration. Some of the processors provide result operands and some perform operations on source operands. A multiconnect register stores the operands at addressable locations. An instruction unit counts iterations and gives source and result address offsets relative to a modifiable pointer. An invariant address unit assigns a value to the modifiable pointer according to which iteration is being performed and combines the pointer with the offsets to provide source and destination addresses. An epilog counter stores a count of ending iterations in which progressively fewer instructions are executed in each succeeding iteration.