TESTABLE RAM ARCHITECTURE IN A MICROPROCESSOR HAVING EMBEDDED CACHE MEMORY

Patent №

US 5,249,281

Granted

1993-09-28

Filed 1990

Owner

LSI LOGIC CORPORATION, A CORP. OF DE

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

07596986

A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.

AI hardwareG06F 11/2236G06F 11/2733G06F 12/0802G11C 29/24G11C 29/36G11C 29/48G01R 31/31905

AI classification

AI hardware0.70
Natural language0.01
Speech0.01
Planning0.00
Evolutionary computation0.00
Knowledge representation0.00
Machine learning0.00
Vision0.00

Ownership

LSI LOGIC CORPORATION, A CORP. OF DE

assignment · 54820029

Assignors

FUCCIO, MICHAEL, DESAI, SANJAY

On an employer assignment, the assignors are typically the inventors.

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