CACHE MEMORY SYSTEM

A tag section of a cache memory system comprises a memory for storing a plurality of first address data read out with a small amplitude (e.g., 0.2 Vpp), a circuit for comparing a plurality of second address data, input from the outside of the system, with the plurality of first address data, and providing comparison results with a second amplitude (e.g., 0.8 vpp), an OR logic circuit including a plurality of bipolar transistors having bases to which the comparison results are respectively supplied, collectors connected to a first voltage source, and emitters which are all connected to an emitter dot line, and a circuit for measuring the potential of the emitter dot line by using a reference voltage to determine that all the first and second data coincide with each other. Since a read operation with respect to each tag memory and most hit detecting operations are performed with small-amplitude signals of the ECL level, a high-speed operation can be performed.