Patent US 5,454,089

Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation. If a branch bypass does not occur, then the branch address is driven from the branch register.