DEBUG SYSTEM WITH HARDWARE BREAKPOINT TRAP

Disclosed herein is sophisticated but low-cost debug hardware which may be used to identify the root cause of a functional or electrical problem in a microprocessor chip. The debug hardware provides for generating a hardware breakpoint trap (HBT) in response to programmed combinations of internal signal triggers, and if desired, a HBT may be delayed through one or more occurrences of a programmed trigger combination via use of an iteration counter. Apparatus for generating and handling a HBT may comprise one or more trigger means, one or more event generation means, and debug software comprising code for 1) preserving the current architected state of a microprocessor upon generation of a HBT, 2) vectoring to and initiating execution of trap handler code, and 3) restoring said preserved current architected state after said trap handler code has been executed. Each of the trigger means is implemented internally to the microprocessor so as to monitor signals of the microprocessor and generate a trigger as programmed values of the signals are detected. Each of the event generation means is also implemented internally to the microprocessor, and may be used to generate a HBT in response to a programmed combination of the number of triggers generated by said trigger means. The debug software is stored in one or more memories accessible to, but possibly external to, the microprocessor.