DCT/IDCT CIRCUIT

A Discreet Cosine Transform (DCT) circuit consisting of a pipe-lined Single Instruction stream, Multiple Data stream (SIMD) processor array, a transpose memory and a control circuit is provided by exploiting the row-column decomposition method, wherein the processor array is capable of computing one dimensional DCT. In an N-point DCT application, the processor array consists of N PEs (processor elements), each of which can compute a N/2-point inner product. Instead of a conventional Multiplexed Analogue Components (MAC) design, the present DCT circuit computes the N/2-point inner product by a word-parallel bit-serial method, which uses N/2 Read Only Memory (ROM) tables, a Wallace tree and one carry propagate adder. This implementation achieves cost-saving and better timing in comparison to a MAC design. Meanwhile, the circuit also has the advantages of simple data routing, regular structure and modular design, and is suitable for Very Large Scale Integration (VLSI) implementation.