PIPELINED COMPLETION FOR ASYNCHRONOUS COMMUNICATION

Patent №

US 6,038,656

Granted

2000-03-14

Filed 1998

Owner

CALIFORNIA INSTITUTE OF TECHNOLOGY

Lab

—

AI components

ml · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09151334

An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

Machine learning AI hardwareG06F 15/8053G06F 9/3871

Google Patents

AI classification

AI hardware0.70

Machine learning0.63

Evolutionary computation0.00

Natural language0.00

Knowledge representation0.00

Vision0.00

Speech0.00

Planning0.00

Ownership

CALIFORNIA INSTITUTE OF TECHNOLOGY

assignment · 95950699

Assignors

MARTIN, ALAIN J., LINES, ANDREW M., CUMMINGS, URI V.

On an employer assignment, the assignors are typically the inventors.

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Cites (2)

AN ASYNCHRONOUS PIPELINE HAVING CONDITION DETECTION AMONG STAGES IN THE PIPELINEUS 5,574,925 · 1996 Patent US 5,732,233US 5,732,233

Cited by (65)

SYSTEM AND METHOD FOR CRYOGENIC HYBRID TECHNOLOGY COMPUTING AND MEMORYUS 10,950,299 · 2021 METHODS AND DEVICES FOR TREATING AND PROCESSING DATAUS 9,075,605 · 2015 LOGICAL CELL ARRAY AND BUS SYSTEMUS 9,047,440 · 2015 DATA PROCESSING METHOD AND DEVICEUS 8,914,590 · 2014 METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURESUS 8,869,121 · 2014 DATA PROCESSING DEVICE AND METHODUS 8,812,820 · 2014 RECONFIGURABLE SEQUENCER STRUCTUREUS 8,803,552 · 2014 CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTSUS 8,726,250 · 2014 RECONFIGURABLE ELEMENTSUS 8,686,475 · 2014 RECONFIGURABLE ELEMENTSUS 8,686,549 · 2014 LOGIC CELL ARRAY AND BUS SYSTEMUS 8,471,593 · 2013 FLOW AND CONGESTION CONTROL IN SWITCH ARCHITECTURES FOR MULTI-HOP, MEMORY EFFICIENT FABRICSUS 8,467,342 · 2013 PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATIONUS 8,468,329 · 2013 DEVICE INCLUDING A FIELD HAVING FUNCTION CELLS AND INFORMATION PROVIDING CELLS CONTROLLED BY THE FUNCTION CELLSUS 8,429,385 · 2013 METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURESUS 8,407,525 · 2013 RECONFIGURABLE SEQUENCER STRUCTUREUS 8,310,274 · 2012 A PROCESSOR CHIP INCLUDING A PLURALITY OF CACHE ELEMENTS CONNECTED TO A PLURALITY OF PROCESSOR CORESUS 8,312,200 · 2012 METHODS AND DEVICES FOR TREATING AND PROCESSING DATAUS 8,312,301 · 2012 PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATIONUS 8,301,872 · 2012 RECONFIGURABLE GENERAL PURPOSE PROCESSOR HAVING TIME RESTRICTED CONFIGURATIONSUS 8,281,108 · 2012 METHOD AND DEVICE FOR PROCESSING DATAUS 8,281,265 · 2012 HARDWARE DEFINITION METHOD INCLUDING DETERMINING WHETHER TO IMPLEMENT A FUNCTION AS HARDWARE OR SOFTWAREUS 8,250,503 · 2012 METHOD FOR INTERLEAVING A PROGRAM OVER A PLURALITY OF CELLSUS 8,230,411 · 2012 ROUTERUS 8,209,653 · 2012 I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURESUS 8,195,856 · 2012

and 40 more

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