METHOD AND SYSTEM FOR FLEXIBLE CONTROL OF BIST REGISTERS BASED UPON ON-CHIP EVENTS

A method and structure facilitates the debugging and test coverage capabilities of a microprocessor. A microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST) engines is disclosed. The debug block is capable of driving control information out onto a state machine output bus in response to an event and the control information can be selectively used to control signature analysis or recording elements of the microprcessor, such as multiple-input-shift-registers and first-in-first-out devices, that facilitate in the monitoring and debugging of the microprocessor. The signature and recording elements may or may not be contained within the one or more BIST engines and may or may not be used in conjunction with the memory arrays or BIST engine(s) of the microprocessor.