METHOD AND APPARATUS FOR PROVIDING VISIBILITY AND CONTROL OVER COMPONENTS WITHIN A PROGRAMMABLE LOGIC CIRCUIT FOR EMULATION PURPOSES

One embodiment of the present invention provides an apparatus that selectively provides visibility and control over components within a programmable logic circuit during the process of emulating a logic circuit. The apparatus includes an input mechanism that receives a specifier for a memory element to be accessed during emulation of the logic circuit. This memory element resides within a design specifying logic to be programmed into the programmable logic circuit. The apparatus also includes a design modification mechanism that modifies the design so that the memory element is accessible through I/O pins on the programs logic circuit, and a programming mechanism that programs the modified design into the programmable logic circuit. The apparatus additionally includes a testing mechanism that tests the programmable logic circuit and accesses the memory element during the testing. In one embodiment of the present invention, the memory element is a register. In one embodiment of the present invention, the programmable logic circuit includes a field programmable gate array (FPGA). In one embodiment of the present invention, the design modification mechanism is configured to map the memory element into an address space of a bus that is coupled to the I/O pins so that the memory element can be accessed by a testing program. In one embodiment of the present invention, the testing mechanism is configured to access the memory element by reading a value from the memory element or by writing a value into the memory element.