METHOD FOR UPPER LEVEL CACHE VICTIM SELECTION MANAGEMENT BY A LOWER LEVEL CACHE

Patent №

US 6,446,166

Granted

2002-09-03

Filed 1999

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09340073

A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.

AI hardwareG06F 12/0811G06F 12/0897G06F 12/12

AI classification

AI hardware0.71
Natural language0.00
Vision0.00
Machine learning0.00
Planning0.00
Speech0.00
Evolutionary computation0.00
Knowledge representation0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 100670420

Assignors

ARIMILLI, RAVI K., CLARK, LEO J., DODSON, JOHN S., GUTHRIE, GUY L.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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