FRAMEWORK FOR RULES CHECKING UTILIZING RESISTOR, NONRESISTOR, NODE AND SMALL NODE DATA STRUCTURES
Patent №
US 6,523,152
Granted
2003-02-18
Filed 2000
Owner
HEWLETT-PACKARD COMPANY
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09521866
An Electrical Rules Check (ERC) methodology ensures the quality of an electrical circuit through the creation of up to four different data structures, corresponding to one or more nodes, one or more small nodes, one or more non-resistor elements, and one or more resistor elements of the circuit, that are used by an ERC program running on one or more processors. The creation of data structures for small nodes and resistor elements in which less information need be stored for use by the ERC program minimizes the amount of data storage that must be utilized.
AI classification
Ownership
HEWLETT-PACKARD COMPANY
assignment · 111260105
Assignors
RAKEL, TED SCOTT, MCBRIDE, JOHN G.
On an employer assignment, the assignors are typically the inventors.