CAPACITORLESS DRAM GAIN CELL

A nondestructive read, two-device gain cell for a DRAM memory, based on conventional complementary metal oxide technology is disclosed. The charge is stored on the gate of a first MOSFET, with a second MOSFET connected to the gate for controlling the charge in accordance with an information bit. Depending on the stored charge, the surface under the gate of the first MOSFET is in a depletion or weak inversion condition. For both conditions, the first MOSFET is “off-state.” The first MOSFET causes a bipolar current flow when it is in a weak inversion condition, due to a “read” forward bias of the source to body junction. The bipolar current substantially depends on current gain, thereby multiplying the effective charge read from the first MOSFET.