DESIGN METHOD AND APPARATUS FOR A SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISING CHECKERS VERIFYING THE INTERFACE BETWEEN CIRCUIT BLOCKS
Patent №
US 7,107,569
Granted
2006-09-12
Filed 2004
Owner
HITACHI, LTD.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10770479
A functional block for verifying correct interface operation of any functional block is generated from interface description and installed on a LSI chip. To accomplish this, from the interface description, hardware description of a synthesizable interface checker is generated. Means for selecting interface functions to be checked is provided, thereby making it possible to reduce the overhead of circuits to be installed on the LSI.
AI hardwareG06F 30/30
AI classification
AI hardware0.80
Knowledge representation0.02
Machine learning0.01
Evolutionary computation0.01
Natural language0.01
Speech0.00
Vision0.00
Planning0.00
Ownership
HITACHI, LTD.
assignment · 149580776
Assignors
ITO, MASAKI
On an employer assignment, the assignors are typically the inventors.
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