METHOD AND APPARATUS FOR PERFORMING REGISTER RETIMING IN THE PRESENCE OF TIMING ANALYSIS EXCEPTIONS
Patent №
US 9,710,591
Granted
2017-07-18
Filed 2015
Owner
ALTERA CORPORATION
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14627191
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
AI classification
Ownership
ALTERA CORPORATION
assignment · 349930009
Assignors
DERISAVI, SALEM, CHIU, GORDON RAYMOND, GAMSA, BENJAMIN
On an employer assignment, the assignors are typically the inventors.