Patent №
US 7,463,523
Granted
2008-12-09
Filed 2005
Owner
KABUSHIKI KAISHA TOSHIBA
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11236671
A semiconductor memory device includes a semiconductor layer; a source layer provided in the semiconductor layer; a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer; a gate insulation film provided on the body region; and a gate electrode provided on the gate insulation film, wherein data are written or read out by accumulating electric charge in the body region or releasing electric charge from the body region, and wherein a difference between the potential VSR of the source layer in a data-retaining period and the potential VGR of the gate electrode in the data-retaining period is smaller than a difference between the potential VSW of the source layer in a data write period and the potential VGR.
AI classification
Ownership
KABUSHIKI KAISHA TOSHIBA
assignment · 173090912
Assignors
SHINO, TOMOAKI
On an employer assignment, the assignors are typically the inventors.