LOGIC ANALYZER SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

Patent №

US 7,743,296

Granted

2010-06-22

Filed 2007

Owner

LATTICE SEMICONDUCTOR CORPORATION

Lab

AI components

2

vision · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11691040

A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.

VisionAI hardwareG06F 30/331H03K 19/177

AI classification

AI hardware0.95
Vision0.55
Natural language0.37
Knowledge representation0.00
Machine learning0.00
Evolutionary computation0.00
Planning0.00
Speech0.00

Ownership

LATTICE SEMICONDUCTOR CORPORATION

assignment · 190640401

Assignors

PIERCE, DAVID, HAMMER, MICHAEL, CASLIS, BRIAN M.

On an employer assignment, the assignors are typically the inventors.

© 2026 NYSGPT2525 LLC