GAINING ACCESS TO INTERNAL NODES IN A PLD

Patent №

US 6,754,862

Granted

2004-06-22

Filed 2001

Owner

ALTERA CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09802480

Internal registers of a PLD are exposed for debugging using a JTAG port and a scan chain. The user of a PLD identifies registers at the source code level. These registers are automatically inserted in a scan chain. An EDA software tool provides a means of choosing a register from the electronic design. The EDA tool connects the selected register to the JTAG scan chain and passes information to the software about the location in the scan chain. The EDA tool provides for scanning of the chain under automatic or manual control. The selected nodes are extracted from the chain and displayed in a user-specified format. Registers in encrypted blocks are exposed. The vendor of the block decides which registers are of importance. Once selected, the vendor creates a “debugging” file which is delivered to the customer along with the encrypted block. The debugging file contains the names of the registers, their data type, and their symbolic values.

AI hardwareG06F 30/331G01R 31/318516

AI classification

AI hardware0.91
Knowledge representation0.02
Natural language0.00
Evolutionary computation0.00
Vision0.00
Planning0.00
Machine learning0.00
Speech0.00

Ownership

ALTERA CORPORATION

assignment · 119420703

Assignors

HOYER, BRYAN H., FAIRMAN, MICHAEL C.

On an employer assignment, the assignors are typically the inventors.

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