YIELD BASED RETARGETING FOR SEMICONDUCTOR DESIGN FLOW

Patent №

US 7,784,019

Granted

2010-08-24

Filed 2007

Owner

CADENCE DESIGN SYSTEMS, INC.

Lab

AI components

1

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11934047

A method for modifying an integrated circuit design layout is presented and can include placing a plurality of target points in the proximity of a polygon representing a portion of the integrated circuit design; modifying the target point placement for some or all of the placed target points; fitting a curve to the target points; and redefining the portion of the integrated circuit as a contour defined by the fitted curve to modify the design layout. In some applications the modified design layout can be used as a target for an optical proximity correction algorithm or for other purposes.

PlanningG06F 30/39G06F 2119/18Y02P 90/02

AI classification

Planning0.97
AI hardware0.03
Evolutionary computation0.01
Natural language0.00
Machine learning0.00
Knowledge representation0.00
Vision0.00
Speech0.00

Ownership

CADENCE DESIGN SYSTEMS, INC.

assignment · 212220748

Assignors

ZACH, FRANZ

On an employer assignment, the assignors are typically the inventors.

From the same owner

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