Patent №
US 11,630,938
Granted
2023-04-18
Filed 2019
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
16673792
Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.
AI classification
Planning1.00
AI hardware0.04
Knowledge representation0.01
Evolutionary computation0.00
Natural language0.00
Machine learning0.00
Speech0.00
Vision0.00
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 509100577
Assignors
LORENZINI, STEFANO, ARMATO, ANTONINO
On an employer assignment, the assignors are typically the inventors.
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