PACKET PROCESSING IN A PARALLEL PROCESSING ENVIRONMENT

Patent №

US 8,194,690

Granted

2012-06-05

Filed 2007

Owner

TILERA CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11753325

Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.

AI hardwareH04L 49/90H04L 47/60H04L 47/52

AI classification

AI hardware0.95
Machine learning0.28
Vision0.10
Knowledge representation0.07
Planning0.02
Natural language0.00
Evolutionary computation0.00
Speech0.00

Ownership

TILERA CORPORATION

assignment · 265520802

Assignors

STEELE, KENNETH M., AGGARWAL, VIJAY

On an employer assignment, the assignors are typically the inventors.

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