TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS

Patent №

US 8,201,111

Granted

2012-06-12

Filed 2011

Owner

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Lab

—

AI components

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13195907

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Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

PlanningG06F 30/367G06F 30/398

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Planning0.55

Machine learning0.28

Natural language0.00

AI hardware0.00

Knowledge representation0.00

Vision0.00

Evolutionary computation0.00

Speech0.00

Ownership

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

assignment · 266830924

Assignors

HOU, YUNG-CHIN, CHENG, YING-CHOU, LIU, RU-GUN, LAI, CHIH-MING, CHENG, YI-KAN, LIN, CHUNG-KAI, CHAO, HSIAO-SHU, YEH, PING-HENG, WU, MIN-HONG, KU, YAO-CHING, OU, TSONG-HUA

On an employer assignment, the assignors are typically the inventors.

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Cites (32)

MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATIONUS 7,954,072 · 2011 SCHEMA-BASED PORTAL ARCHITECTURE FOR ASSESSMENT AND INTEGRATION OF SILICON IPSUS 7,870,381 · 2011 ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTIONUS 7,865,864 · 2011 METHOD FOR DETECTION AND SCORING OF HOT SPOTS IN A DESIGN LAYOUTUS 7,685,558 · 2010 METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATAUS 7,570,796 · 2009 SYSTEM FOR DESIGNING INTEGRATED CIRCUITS WITH ENHANCED MANUFACTURABILITYUS 7,523,429 · 2009 IDENTIFYING LAYOUT REGIONS SUSCEPTIBLE TO FABRICATION ISSUES BY USING RANGE PATTERNSUS 7,503,029 · 2009 QUALITY PROGNOSTICS SYSTEM AND METHOD FOR MANUFACTURING PROCESSESUS 7,493,185 · 2009 SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD, AND SOFTWARE PRODUCT FOR THE SAMEUS 7,475,377 · 2009 ADAPTIVE CORRELATION OF PATTERN RESIST STRUCTURES USING OPTICAL METROLOGYUS 7,440,881 · 2008 SIMULATOR FOR A CHEMICAL MECHANICAL POLISHINGUS 7,363,207 · 2008 DELTA INFORMATION DESIGN CLOSURE IN INTEGRATED CIRCUIT FABRICATIONUS 7,360,191 · 2008 METHOD AND SYSTEM FOR INCREASING PRODUCT YIELD BY CONTROLLING LITHOGRAPHY ON THE BASIS OF ELECTRICAL SPEED DATAUS 7,325,224 · 2008 HIERARCHICAL DETERMINATION OF FEATURE RELEVANCYUS 7,313,279 · 2007 DIAGNOSTIC DATA DETECTION AND CONTROLUS 7,181,365 · 2007 MULTIVARIATE CONTROL OF SEMICONDUCTOR PROCESSESUS 7,151,976 · 2006 METHOD AND APPARATUS TO ENABLE ACCURATE WAFER PREDICTIONUS 7,144,297 · 2006 PREDICTION METHOD AND APPARATUS OF A PROCESSING RESULTUS 7,139,620 · 2006 SYSTEM AND METHOD FOR REAL-TIME FAULT DETECTION, CLASSIFICATION, AND CORRECTION IN A SEMICONDUCTOR MANUFACTURING ENVIRONMENTUS 6,980,873 · 2005 COMPUTER-IMPLEMENTED METHOD AND CARRIER MEDIUM CONFIGURED TO GENERATE A SET OF PROCESS PARAMETERS FOR A LITHOGRAPHY PROCESSUS 6,968,253 · 2005 PROBABILITY CONSTRAINED OPTIMIZATION FOR ELECTRICAL FABRICATION CONTROLUS 6,959,224 · 2005 METHOD AND APPARATUS FOR PREDICTING ELECTRICAL PARAMETERS USING MEASURED AND PREDICTED FABRICATION PARAMETERSUS 6,917,849 · 2005 CORRELATING AN INLINE PARAMETER TO A DEVICE OPERATION PARAMETERUS 6,810,296 · 2004 DYNAMIC TARGETING FOR A PROCESS CONTROL SYSTEMUS 6,773,931 · 2004 MULTIVARIATE STATISTICAL PROCESS ANALYSIS SYSTEMS AND METHODS FOR THE PRODUCTION OF MELT POLYCARBONATEUS 6,549,864 · 2003

and 7 more

Cited by (1)

Prioritized Design for Manufacturing Virtualization with Design Rule Checking FilteringUS 9,026,970 · 2015

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